Fast bitset decoding using Intel AVX-512

This brings a huge simplification to any loop which must process arrays of variable sizes and alignments.

With SSE or AVX you have to write very complex prologue and epilogue code for loops, to handle the sizes that are not a multiple of the register size and to cope with various alignments. A compiler may be not smart enough to add such code, so it may fail to vectorize a loop, while when the code is written by hand it is hard to avoid bugs.

With AVX-512 handling any size or alignment is trivial and it can also be done automatically by compilers when vectorizing loops.

The second feature is that in AVX-512 there are both gather load and scatter store instructions, which simplify the manual or automatic vectorizing of loops that must access some data structures that do not have the layout required by the SIMD instructions.

Also AVX-512 has a more complete and flexible set of instructions to do various permutations between the parts of the SIMD registers, which also allow the vectorization of some loops that would have been difficult to convert to SIMD instructions when using SSE and AVX.

The net effect of all these features is that many loops that were not worthwhile to convert to SIMD with SSE or AVX, because the resulting programs would have been very complex and would have contained a large number of instructions, can be converted to AVX-512 with little effort and the resulting program has much less instructions than in the SSE/AVX version.

For the loops that are easy to convert to SIMD, e.g. they access only aligned arrays whose size is a multiple of the SIMD register size and there is no need to access other kinds of data structures, e.g. arrays of structures with heterogeneous members, AVX-512 may have no advantage over AVX, except if the target CPU happens to have double throughput with 512-bit registers (true for a part of the server/workstation Intel CPUs).