There was a talk at Kicon that touched on this:
https://www.youtube.com/watch?v=WErQYI2A36M
At some point for large enough designs, it's hard to validate that pins match up to signals. Though for small designs I think you're right.
https://www.youtube.com/watch?v=WErQYI2A36M
At some point for large enough designs, it's hard to validate that pins match up to signals. Though for small designs I think you're right.
TL;DW the tool is named Skidl ans uses Python to generate net lists for KiCAD. https://github.com/devbisme/skidl
hmm.. maybe that's ok if they don't go too overboard and encourage a functional style
> uses & as an in-place, mutating operator
that's it, I'm out of here
In this case it's simple to do:
net1 = pin1, pin2, pin3
design = net1, net2, net3...For example, the madness with the schematic he shows in that video for all of the by pass caps is something you'd never really see in an IC design. The cap would be placed in the schematic hierarchy either right at the voltage regulator or right at the circuit where its needed. But on PCB schematics you see that kind of thing all the time.
Part of the problem may be that with an IC you can easily simulate anything. The whole workflow is built around it. For a PCB, outside of using models for standard analog building blocks via spice simulator, it's a lot harder to verify your design.