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Makes me wonder how Verilog isn’t used as a netlist format for PCB schematics. It’s used all the time as an interchange format for netlists from synthesis to APR, netlists of analog schematics, etc. Could just as easily be deployed to board schematics.

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It's totally valid as a netlist for PCB schematics. Some folks have crammed PCB components through a pure verilog tool chain.

But it turns out that 'a standard way to type out a netlist' is not the main thing an electrical designer needs from a language to be productive.

VHDL has been used for design and simulation of boards (by myself and others).

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