This is yet another market that C++ seems to be slowing winning the hearts of the industry, as even with its issues, it is a much easier development experience than dealing with traditional FPGA workflows and programming languages.
As for HDLs, it is clear it will still take time, however Intel and Xilink seem keen in giving an helping hand.
FGPA using c/c++ for high level design has been in existence for years, not really caught on, and unlikely will make any dent in the near future.
The C++ being written in this example also feels like it has to be very carefully considered (and with a bunch of pragmas) so it doesn't feel like C++, it feels like a C++ syntax on top of Verilog or VHDL. Maybe this could still be quite useful, though. I guess simulating might be easier when you can start out with C++ code.
What I was referring to was standards like SYSCL, which is basically the competition to CUDA nowadays, and is being embraced, if one believes on Khronos updates.