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Nice, thank you for the notice about the inner layers.

They don't make a big deal about it when they improve the capabilities: in the past they've also improved minimum via ring diameter from 0.45mm to 0.4mm, which doesn't sound like much but it allows you to fit the vias in between 0.8mm pads on inner layers.

Patiently waiting for the day microvias become too cheap to meter.

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I wish they advertised it more! That reduction in annular pad plus the inner player geometry is a game changer. Effectively any 0.8mm pitch bga is completely prototype-able now.

I did a 0.8mm fanout on their older limits, and it was barely doable - the inner balls of the ECP5 FPGAs are all power and ground, and with careful depopulating of the inner layers' annular rings it's possible to get enough working room to make it all fit!

But if you want signals in those inner balls... still pretty tight. And the 15x15 ECP5 is the absolute max this would work for; after that you hit both needing inner layers to route on, and additional ground planes for the outer layers' return current.

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