Camel: CXL-based memory disaggregation framework

Worth clicking for just the image of the memory-board they've built. Unlike most pcb's, it's stark & open, hardly a passive component on it. Really wild to see so much open boardspace. They have 8 dimms here. I suspect it's basically just an FPGA acting as a CXL memory controller, but perhaps there's more.

They compare themselves versus RDMA over Infiniband (56Gbps) which makes sense as it's the competitor. It's not clear to me whether they are using their CXL switch in their tests, or whether the CXL memory is directly attached; I'd be curious to know what the performance hit is for switching. But the idea of massive fan out memory is definitely compelling!

Medium term, I imagine we'll be seeing variants of stuff like this with HBM stacks onboard. See the recent UCIe chiplets alliance[1], with AMD, Intel, TSMC, Samsung, others. To tie it back to my first comment, this would just be a modest modern microminaturization of this wide open sparsely-populated huge PCB... just put this whole thing on chip. It'd make a very large (capacity), very small (footprint) memory module.

It's unsurprising that this company is claiming some patents over this technology even in the press brief. Hopefully the core ideas of CXL are allowed to germinate & grow, without the ecosystem immediately becoming IP overencumbered.

[1] https://www.servethehome.com/universal-chiplet-interconnect-... https://news.ycombinator.com/item?id=30538809 (92 points, 12 days, 26 comments)