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Comment by mhh__ | Hacker News Reader

Ok looks like I was wrong.

Is the openc906 definitely the same design as the one in the D1? It looks like it is but I have been bitten by xyz vs. open-xyz subtlety before.

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The openc906 is just the CPU core, however (and the released C906 Verilog code might have some updates and bugfixes compared to the silicon in the D1).

The English datasheet and user manual for the D1 are available at https://linux-sunxi.org/D1

However, some of the peripheral hardware (such as the video unit/frame buffer) is not documented and the documentation for the C906 CPU core itself is only available in Chinese.

> and the released C906 Verilog code might have some updates and bugfixes compared to the silicon in the D1

Not really, the C906 source code (close-source) is written in Vperl (a custom internal language) which is translated into verilog by an internal tool. The OpenC906 (open-source) is only the generated verilog code from a light version of the C906 Vperl code, with some hand-made modifications/fixes.

The Vperl code and the tools to process it are not made public. However, the code generator leaves the Vperl code in verilog commentaries which gives an idea of the original code, and shows that big chunk of code have been removed/patched by hand.

I've mostly read code from the OpenC910, but I can tell you for sure that the C906 design and the OpenC906 design does not only differ only in some "updates and bugfixes". It's another code generated from a more advanced design which is not open-source

Edit: Not telling that the OpenC906 doesn't give you an idea of how the C906 is made, just that the C906 may contain a lot of differences with the OpenC906 that you don't know.

I see. Thank you for explaining! I didn't realize that the Verilog RTL for the OpenC906 wasn't the actual source code, or that the C906 was different from the OpenC906.

Chinese is the command line of the 21st century. I've had the same difficulty with CKS32 datasheets.

I don't know for sure; even if it purportedly is, there's probably no way to verify that no hardware backdoors have been inserted, if that's your concern. And rebuilding the CPU with your desired modifications would require signing the appropriate agreements with your fab provider of choice and probably a million dollars or so over a year or two. Still, you could probably do cycle-accurate simulations on an FPGA at a lower clock speed, if that's what you're into.

https://www.hackster.io/news/mangopi-mq1-is-an-ultra-compact... claims the Allwinner D1 "is" the "XuanTie C906, which Alibaba's T-Head division recently released under the permissive Apache 2.0 open source license." But of course the author could be mistaken about that.

You can integrate the C910 (should work for the C906 as well) in Olof Kindgren's FuseSoC tool, see https://twitter.com/OlofKindgren/status/1451654866837938186

> Is the openc906 definitely the same design

No, OpenC906 is a light version of the C906 and they only release generated verilog code without any testbench

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