nm notation used to mean the width of the smallest feature that could be made. Even today there are processes such as atomic layer deposition (ALD) that allows singular atom thick features. The difference between nodes now are in shrinking macro features, you don't necessarily make them smaller, more important is density. This is currently done with 3d transistors (finfet) and perhaps in the future going full vertical. When all other optimization have been exhausted it's likely to see multiple layers of stacked transistors simulator to what they are doing with NAND memory chips. Eventually even that will hit a wall due to thermal limitations. Beyond that people have proposed using carbonnano tube transistors. That tech is very early but has been proved to function in labs. If we ever figure out how to manufacture carbon nanotubes chips, it will be truly revolutionary; you could expect at least another 50 years of semiconductor innovation.