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kop316

Am I missing something or is the final source for the caravel user project missing?

I cannot find it here: https://efabless.com/projects/shuttle_name/MPW-1

Nor here (since I think it is by efabless?) https://github.com/orgs/efabless/repositories

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The chip ignite path does not require designs to be published, unlike the Google sponsored MPWx tapeouts.

I get that, but the link literally says: "The Open Source FPGA ASIC". With that in the title, I would expect to be able to find the source of the FPGA.

Required or not, it is desirable.

Looks like this has been put together by Efabless themselves. I dont think the rtl would be too different from OpenFPGA(https://github.com/lnis-uofu/OpenFPGA) married to the caravel f/w.

My guess would be that the first prototype that they made was too buggy to publish. The promise is that they will share the final design, and I am fine with that.

(I am not affiliated with the project, but backed it)

According to this website: MPW-1 had a hold time violation in it's clock tree, so the RISC-V is unusable.

https://www.zerotoasiccourse.com/post/mpw1-bringup/

Yikes. If I'm understanding that correctly every chip that came back from MPW-1 was more or less unusable - they were all required to gate access to I/Os behind the same management processor provided by the company organising the run, and because that management processor was broken they couldn't configure the I/Os to route through to their own designs.

Yeah that is my understanding too. You REALLY don't want a hold time violation, as you have to go in and edit the chip circuitry to fix that.

Update: marcan_42 apparently found it: https://efabless.com/projects/33

I don't think they are the same:

Look at the picture in it versus in the link:

https://groupgets-files.s3.amazonaws.com/Efabless/open-sourc...

They are different. Also, if you go to https://vlsicad.ucsd.edu/Publications/Conferences/383/c383.p...

Figure 6: You can find the image from the link (top left), and the on ehtat you linked (bottom left), so they are two different projects.

Isn't it this one?

https://efabless.com/projects/33

I thought so too, but look at the picture in it versus in the link:

https://groupgets-files.s3.amazonaws.com/Efabless/open-sourc...

They are different.

Also, if you go to https://vlsicad.ucsd.edu/Publications/Conferences/383/c383.p...

Figure 6: You can find the image from the link (top left), and the on ehtat you linked (bottom left), so they are two different projects.

I get the feeling the image from the link might just be wrong, though. It has 3 identical blocks in the user logic area. That doesn't fit the 8x8 FPGA story. There's no factor of 3 there. Maybe they just used a random example built on the same platform?

Edit: yup, they just picked a pretty picture they had of what was apparently the first design in MPW1. You can browse it here:

https://siliconpr0n.org/map/gsky/mpw1-00010001/mz_mit10x/

Almost certainly not the actual FPGA design.

I mean...in my mind, that raises more questions. All of the "Additional Cool stuff" to be implies that it was fabbed out on mpw-1 and they have tested it. Why take a random image then if you have die shots or a picture of the GDS?

Then again, the low power consumption picture looks to be measuring the SPI flash? that is far too little pins for the FPGA.

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