1) The standards body that controls EDIF no longer exists, this could limit the ability to evolve and improve it.
2) Large placed and routed FPGA designs contain a lot of data and rendering it to EDIF would just slow down the process of transferring, parsing, etc. Binary is the way to go (unless debugging, the FPGA Interchange Format offers a human-readable version for that). As a comparison, some of the proprietary vendor design formats can take tens of minutes to load a full design.
3) Expressing the details necessary to reconstruct a placed and routed FPGA circuit would not naturally flow from EDIF. EDIF is good for describing a logical netlist. However, a placed and routed FPGA implementation is the mapping of a logical netlist onto the physical netlist of the FPGA. Building a format suited to FPGA architecture makes expression of these constructs easier and more efficient.
4) Writing and maintaining an EDIF parser/de-parser creates more work than using a schema-based code generator. Although work is still involved when interfacing the tool to the format, it removes a pile of issues associated with text-based formats.
[edit: fixed typo]