How much: it was really low, and easier to get it in practice compared with ST's STM32L chips. I wonder if ST's new U series is using some kind of sub-threshold logic, but I assume Ambiq has the patents..
There have been a couple of experimental processors on which professors have published papers claiming an order of magnitude lower power consumption than Ambiq claims for their chips. Assuming that's true, I don't know how much of that is a question of process variability (e.g., maybe 5% of Ambiq's chips also get such low power consumption) and how much is a question of other engineering compromises (e.g., maybe ARM is a particularly power-hungry architecture, as the lower power consumption of the GD32VF chips suggests, or maybe the experimental chips only worked between 47° and 47.5° and even then they crashed once an hour).
By "really low" do you mean active power more like 1 microwatt, 10 microwatts, 100 microwatts, or a milliwatt?
What I liked is that all peripherals were "low power"- all of them could work when the CPU was off and all could wake the CPU (well it woke on any pending interrupt). So it means it's more likely that the CPU is asleep. With STM32L, only peripherals designated low power would work while the CPU was off.
But actually that number is totally in keeping with what I'd gotten from the Apollo3 datasheet: 33 pJ per Dhrystone "instruction" at 48 MHz and 1.25 DMIPS/MHz is 1.98 mW, and then there's 0.22 mW overhead, so we'd expect about 2.2 mW. 3 is close enough, especially for an earlier-generation chip. You might get an STM32L or an ATMega328 down to a milliwatt or two in run mode, but what (theoretically!) distinguishes the Ambiq chips is not their maximum power draw, but their efficiency per instruction and their deep power down load, which is what determines their power draw at a given computational load.
Limited low-power peripherals can be a huge headache, yeah.
Thank you very much for sharing your knowledge!