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throwaway19937

TL;DR RISC-V doesn't have add with carry.

I'm not a fan of the RISC-V design but the presence or absence of this instruction doesn't make it a terrible architecture.

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_For the purposes of implementing multi-word arithmetic_, which is Torbjörn's whole deal, it kind of does. (Also the actual post subject is "greatly underperforms").

It's meaningless to look at the code in absence an implementation and conclude anything about the performance. He doesn't know what the performance is. Having six instruction vs. two does not mean one is 3X faster than the other. It means nothing at all.

We know enough about the implementation of current RISC-V cores to conclude that they won't be remotely competitive on this one narrow (yet fairly high-impact for some workloads) task. Is it _possible_ to design a core that is competitive on this workload even when handicapped by a limited ISA? Yes, definitely. Have any RISC-V designers shown any interest in doing so yet? No.

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