EDITED: derp, confused: There are POWER Workstations from Raptor Computing Systems (https://www.raptorcs.com/). Talospace are POWER enthusiasts. Thanks amock for the correction.
Can change the endianess at run time.
Their new cache architecture is very unusual. A CPU can use the cache from another chip. Data is stored encrypted.
;)
From an efficiency perspective does that mean the chip has to do both so worst of both worlds?
[I dont know much about the world of cpu design, these might be stupid questions]
The POWER ISA was used in PowerPC which was used for the successors of a few 68k machines (most famously the Macintosh) and in that case the OS was built for big-endian. So having big-endian support was key there.
As for endian shifts, technically every OpenPOWER chip goes big for every OPAL call into the low-level HAL, even if the OS is little. The overhead is minimal. I can't think of much application use for that, though (per-page endianness which some PowerPCs supported is much more useful).
The CPU probably works on just one endianess and convert the data format when reading from memory. The overhead is on kepping track when to do it. But Im speculating, havent looked into this.
The IBM Power is one implementation of the Power ISA.
The chips used on the mars rovers and nintendo Wii as ppc as well.
Yeah, Cortex and NVIDIA cores do (and probably quite some others).
However, Apple-designed recent cores don’t implement big endian support at all.