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Comment by aetherspawn | Hacker News Reader

It's JIT support for the OpenPOWER architecture, which is interesting, but as far as I can tell isn't exactly in wide use right now. At least not where you might need Firefox. https://openpowerfoundation.org/

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EDITED: derp, confused: There are POWER Workstations from Raptor Computing Systems (https://www.raptorcs.com/). Talospace are POWER enthusiasts. Thanks amock for the correction.

How do POWER CPUs compare with ARM, x86, etc?

They are target at datacenters. The last iteration has hardware support to decimal floating point, flexible IO (DDR3, DDR4, DDR5. GDDR6, HBM, PCI5, nvlink), Cores with SMT8, Tbps intra chip network, etc

Can change the endianess at run time.

Their new cache architecture is very unusual. A CPU can use the cache from another chip. Data is stored encrypted.

If the system can change the endianess at any time, does that mean that we should only be using palindromic data? Or is it that we should aim to make everything polyglotic such that both directions have valid but distinct interpretations?

;)

you joke but I learned at a talk comparing genetics to TCP networking (at HOPE, maybe 2014 or 2016, cant find it on the website atm) that DNA is encoded such that it expresses different proteins depending on which direction it is read, might be something to learn from

Interesting. What would the benefit be of changing endianess at runtime?

From an efficiency perspective does that mean the chip has to do both so worst of both worlds?

[I dont know much about the world of cpu design, these might be stupid questions]

It's more something you'd do at boot, if you had to select between an OS built for one or another.

The POWER ISA was used in PowerPC which was used for the successors of a few 68k machines (most famously the Macintosh) and in that case the OS was built for big-endian. So having big-endian support was key there.

IBM i and AIX still run big, in fact. Important for IBM's institutional customers.

As for endian shifts, technically every OpenPOWER chip goes big for every OPAL call into the low-level HAL, even if the OS is little. The overhead is minimal. I can't think of much application use for that, though (per-page endianness which some PowerPCs supported is much more useful).

Network application.

The CPU probably works on just one endianess and convert the data format when reading from memory. The overhead is on kepping track when to do it. But Im speculating, havent looked into this.

Sounds like an architecture full of features you'd like to avoid when you want to run on battery, run as many of them in a datacenter of a given heat dissipation capacity or simply when you're big enough to tailor a CPU design to your needs because you can buy from a chip manufacturing as a service company. Truly an architecture for a different century.

Most company can't afford to make custom chip at 7 nm.

The IBM Power is one implementation of the Power ISA.

The chips used on the mars rovers and nintendo Wii as ppc as well.

armv8 defines the registers for changing endianness too :) https://developer.arm.com/documentation/den0024/a/ARMv8-Regi... Cortex cores at least do support switching endianness for data in userspace (SCTLR_EL1.E0E)

> Cortex cores at least do support switching endianness for data in userspace (SCTLR_EL1.E0E)

Yeah, Cortex and NVIDIA cores do (and probably quite some others).

However, Apple-designed recent cores don’t implement big endian support at all.

The man behind talospace.com doesn't make workstations, he has one from https://raptorcs.com/. He's a PowerPC enthusiast.

Isn't a better allocation of scarce engineering resources on the POWER platform to implement a RDP client to x86 commodity desktop environment for the commercial consumer experience on the web with the benefit of offsetting and isolating potential security breach to that environment? Has anyone made the POWER CPU a raw node for crunching styled on the Plan 9 idea of cpu% ?

I'm missing a lot of context. Can someone explain why POWER9 is interesting?

Is OpenPOWER trying to compete with RISC-V? Whats the benefit compared to modern ARM or x86_64 silicon & ISAs?

POWER9 is interesting (compared to RISC-V) because, right now, you can buy up to a 24 core, SMT4 system (96 threads), running dual CPU sockets if you like, and supporting up to 1 TB of memory per socket, with a maximum boosted clock speed of 3.8 GHz.

All this with fully open firmware, and an open ISA (as of the last couple years). The CPU implementation itself is not open, but all firmware and procedures for initializing the CPU are open. For people interested in that sort of thing, it's appealing as a practical computer with a full PCIe implementation with actually decent performance, compared to essentially every other open source platform.

In fact, you could get a Talos II with dual 22-core CPUs for a whopping 176 threads, even. Raptor has them in stock.

Are the prices of these CPUs comparable to x86 CPUs with similar performance?

In a sense they are, because with those core counts, you're comparing to Epyc and Xeon, which are similarly very expensive.

What they're really missing is a midrange product for a midrange price. I can't blame them for avoiding the low end, but can't I get anything for less than $2000?

I've just tried looking on ebay. Nothing is to be found at decent (as in decent for tinkerers) prices.

Catch 22: Either the hardware could still be used in some system, so used stuff is expensive because some companies pay through the nose for spares, or the hardware is way too old for that, in which case it's an expensive collector's item. If it's very old and common it goes in the crusher.

This seems to be universally true for all kinds of UNIX workstations and servers.

> If it's very old and common it goes in the crusher.

Repeat until the hardware is rare and worth something?

This is what Microwatt is intended to address, though you have to synthesize it yourself. With luck Arctic Tern will give you the playaround board you'd like. https://www.talospace.com/2021/10/first-flight-of-kestrel-fp...

While you're right, that's certainly not by choice but rather stems from the fact that right now, workstation-class OpenPOWER boards are a rather small market. You have to design the board for this server-class chip and break even on the costs for that + manufacturing a board that can actually hold these kind of chips.

So while it's unfortunate, it's not a case of ignoring the low end deliberately but mostly flows from the economic realities of not having anywhere near the addressable market of x86 or ARM. The small community of ppc64(le) enthusiasts is very much hoping for a future where this changes, however small that chance might be...

They’re more expensive, especially factoring in the motherboard. But as a sibling points out, it’s not like HEDT is inexpensive from any vendor.

and you can get a 64 core AMD Threadripper 3990X with 128x PCI-e v4 which makes the Talos II very moot.

When did they make Threadripper open source?

Neither processor is open source

Precisely. Since there's no equivalent of the Power ISA in "x86 land", it's hard to make a direct comparison (I don't believe that formally Intel or AMD consider themselves to share an architecture, and they both have slightly different instruction sets), but the closest comparison would be if AMD or Intel released the source code for PSP or ME respectively, along with all other ancillary firmware and documentation for the bring-up procedures so that, without an NDA or business agreement, a third party could design a motherboard around a Threadripper or Xeon CPU, provide that to a customer, and allow the customer to make modifications to the firmware running on that motherboard.

While that may be true from a cost/performance point of view, the point of the Talos is to keep the system as transparent as possible (schematics, open source firmware etc.). If that is not a concern for you it doesn't matter I guess. But for some people it is, and the Talos is the most attractive board out there from a performance point of view if that kind of transparency is a thing for you.

I don't think you understand the point of the talos

The customers picking up Talos II boards won't be interested until you can show them a threadripper/epyc system with coreboot.

IIRC some of the latest AMD boards to end up with coreboot support is using opterons from 2011-2013.

> you can buy up to a 24 core, SMT4 system (96 threads)

For what it's worth:

   $ lscpu | head -5
   Architecture:          ppc64le
   Byte Order:            Little Endian
   CPU(s):                160
   On-line CPU(s) list:   0-159
   Thread(s) per core:    4

You can get SMT8 if you're IBM. Unsure why they don't allow cores to do it without their blessing.

It's trying to compete with x86.

It is interesting as Raptor is one of the few production ready commercial computing hardware providers that offers full source code of its firmware.

https://git.raptorcs.com/git/

> Can someone explain why POWER9 is interesting

From my point of view it is interesting because it provides an alternative to x86 and ARM. The more competition, the better. Competition will push the hardware forward. Imagine we only had only one CPU architecture and one CPU maker.

We have far less CPU architectures than we used to have.

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