Disabling the E-cores apparently activates AVX-512. So it was planned and engineered to be there all along, but was disabled to match the marketing talking points. [https://www.phoronix.com/vr.php?view=30664]
Beyond that, AVX-512 is not POR. It's not validated, checked for IEEE accuracy, and YMMV on whether it works at what frequency with the correct outputs.
Source: AnandTech.... where I wrote about it :)
if you wrote it, it I wouldn't count it as a source /s
isn't that than a bit risky to put something into the bios which might disable intels advances? and especially if not even intel tested it correctly? I mean as a consumer what would happen if I enable it and something breaks?
A shame because the ADL AVX512 units are much more efficient.
Wouldn't an illegal instruction fault suffice to flag a thread running on a mismatched core and allow it to be moved to a suitable one? Or do they lose state when the fault occurs?
X86 doesn’t make that easy.
I wouldn't be surprised if the x86 would let us down here however. Wouldn't be the 8367th time.
Then there is the issue with new instructions that get added.
Yes, you need OS support, but then again, you need support for the ThreadDirector anyway.
OTOH, this could allow us to have very heterogeneous processors in a single system, each with an ISA tailored to a kind of task and the OS knowing which core can run which program.
Linux and Windows both have partitioned schedulers, available through per-process and per-thread affinity masks. So it doesn't seem like it should be all that hard to implement. Its "just" a matter of expressing the process's (thread's?) requirements.