Twice as many channels so twice as many cache misses in flight. The Anandtech shows significant gains on multi core workloads. So the I9-12900K with DDR4 shows 61.33 int, 59.55 FP. With DDR5 it gets 80.53 Intel and 81.85. Some of that is increased bandwidth, but having more memory requests in flight helps as well.

Imagine all the cores generating cache misses and you have 2 channel of memory. When a channel handles a transaction it's unavailable for 40 ns (keep in mind that @ 3GHz with 2 instructions per cycle that's 240 instructions per core).

Now with 4 channels you can have twice as many transactions in flight and your cores spend less time idle and waiting on memory.

So over a 30% increase in performance when going from DDR4 to DDR5, of course this doesn't matter if your application has a high rate of cache hits.

DDR5 has more future promise, whether that's lower power, higher bandwidth, higher capacity, maybe lower latency too. There's something about DDR5 requiring ECC, but it's not clear if that includes actual CPU/OS reporting or if it's internally using ECC but with no error reporting.

But, I'm not sure how much of that shines through in the first DDR5 product vs mature DDR4 products. Now is the part of the cycle where the old memory is still high volume and the new memory is starting to ramp up; in not too long, we'll have the part of the cycle where they made too much of the old memory and prices drop and it's time to scoop up all the old memory you'll ever need.

One big thing is better resistance to cosmic ray bitflips due to the on-chip error protection. (Different from ECC, all DDR5 gets it.) Hopefully rowhammer style trickery is effectively quashed now.

I asked myself the same thing when DDR4 came out. I was looking forward to skipping it, but Ryzen was able to unofficially use ECC ram so that intrigued me. DDR5 will be able to have larger sizes for ram as well if I remember correctly.