It's true that SystemVerilog fixed a lot of Verilog's deficiencies and took it more in the direction of VHDL. But a lot of free tools don't support SystemVerilog.
Thanks!
What I meant were the free toolchains provided by all of the FPGA vendors. They typically support SystemVerilog in synthesis and modelsim as far as I have seen.
Indeed I'd say SystemVerilog is doing better on that front, as Verilator (https://www.veripool.org/verilator/) supports SystemVerilog and is probably the best open source tool for 'real' HDL work (note the number of industrial users).