I come from a VHDL background (the industry I work in is purely VHDL), but recently I've been enjoying Systemverilog in my personal projects and it fixes a lot of these issues!

You can even do:

  typedef enum bit[1:0] {

    my_one, my_two, my_three, my_four

  } my_enum;

  typedef struct packed {

    my_enum b,

    bit [3:0] x

  } my_struct

  my_struct.b <= my_three;

etc...

It's been a nice path since I last dealt with Verilog. The concept of interfaces makes struct/vector input/output even nicer.