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Comment by ncmncm | Hacker News Reader

I find my enthusiasm for RISC-V materially reduced by its appalling lack of a base POPCOUNT instruction. Its lack makes my favorite optimizations annoyingly pessimal.

I understand that, someday, higher-end realizations will begin to ship with various "B" subsets implemented, but "portable" builds will tend to avoid relying on those for an appallingly long time after. (E.g. MSVC and Gcc still do not generate POPCNT instructions, on amd64, unless you specifically identify a post-2004 target.)

I will nonetheless be excited to learn of the first chip that does ship with the full raft of B instructions.

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https://github.com/riscv/riscv-bitmanip/blob/main/bitmanip/_...

I cannot tell what this means.

The B-extension, which likely all desktop class CPUs will have (and probably others too?) has most of the bit manipulation instructions.

There is also a vector extension, crypto extension and even a 128-bit computer (Q-extension)!

It's a link to the proposal for popcount in the bitmanip extension.

I get that. But I said myself that the (optional!) B extension defines a popcount instruction. Does the linked page indicate anything further? Does it say RV64 chips are in fact required to implement the instruction? Or, what do the checkmarks indicate?

FWIW, RISC-V does have a invalid instruction trap mechanism that can be used to provide a software implementation of missing instructions. So at least if the platform provides a software implementation of the B instructions, user code can still use them (much more slowly, of course).

Emulated B extension instructions would be no better than a cruel joke: "Ha, you thought you were optimizing? Here, see how you like extra-super-slow, instead!"

Zba, Zbb, Zbc, Zbs (BitManip) have been approved by "Architecture Review" thus I assume they close to being ratified. Probably one of the first new extensions to be available for RISC-V.

Because it's not ratified the BitManip extensions are not listed in any RISC-V Profiles as supported (or required). Platforms specification is also not requiring it.

Note that the next Profiles will be for 2022, thus any extension ratified before that most likely will appear in a new profile (i.e. as supported, non-conflicting extension) in some set.

OK, so does the "RV64" checkmark on the page mean anything at all?

RV64 on that page refers to the fact the instruction can be implemented (as part of the B extension) on 64 bit RISC-V. RISC-V itself has a well-defined system of base ISA + extensions as explained in section 1.3 of the user specification, available from here: https://riscv.org/technical/specifications/

The bit manipulation extension was released as a draft for a public review.

See the thread here: https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/YiK...

I'm disappointed that zip and unzip are only available on RV32. It's great to be able to create Z-order indexes with a single instruction. I was surprised they had these and then disappointed they're on on RV32.

What does "only available on RV32" mean? Not proposed for smaller configurations?

So, still just a draft. Public comment period ended before August... What is next? Is there any target release date?

IMO RISC-V is rather targeting ARM's niche than that of Intel/AMD, so custom builds will be a more common scenario than distributing binaries.

6.7 billion chips/quarter is "niche"?

niche the noun, not the adjective.

Could you give an example of how you'd use POPCOUNT in an optimization?

See puzzlegen.cc in https://github.com/ncm/nytm-spelling-bee/

Order of magnitude improvement.

BTW, the key line is #45, or line #42 in the Rust version.

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