[1] https://www.wired.com/story/keep-pace-moores-law-chipmakers-...
[2] https://www.tomshardware.com/news/amd-epyc-processor-models-...
[3] https://www.wired.com/story/keep-pace-moores-law-chipmakers-...
Given that this is a trade-ish publication, I think writers/editors will more or less assume their audience understands the smackdown that AMD has been laying on Intel and AMD's chiplet strategy.
Even when Intel moves to heterogeneous dies, that won't actually be a first for them, even in the modern era. Several early i3/i5/i7 models had one die with two cores and another die that handled memory and I/O.
My comment started with that phrase because that's what it was about, but I guess the wording confused people?
But this story is about Intel. Though it depends on how you define "chiplet". In this article it looks like 4 identical chips wired on a package each with their own IO and memory controllers. That's very different from from AMD's core chips wired to an IO chip, and is nothing new for Intel. https://en.wikipedia.org/wiki/Multi-chip_module
It's the expected response from Intel when they are unable to compete on throughput per socket with a single chip (they went to DCMs during the period of Opteron dominance too). I don't know what the story is really -- they said the latency was too high to do this before but they've already done something effectively the same (and multi socket SMP systems have even higher chip to chip latency again, so clearly it can be done). I guess they just improved the on package interconnect performance a bit, but almost certainly they would have done a multi chip to compete with AMD even if they were not able to improve that latency.
As I said, "chiplet" just depends on a definition, there is really no good single one. Almost certainly the dies could be used standalone, and it wouldn't be surprising if some were for low end SKUs (modulo the statement in the article that they won't for this generation) -- there are some mesh IOs on some length about 1/2 the die on two edges, that's it. Not much area.
https://www.pcgamer.com/uk/intel-slide-criticizes-amd-for-us...
It’s not something to brag about.
Intel went the EMIB route to route through embedded silicon but people need to be reminded on HN that chiplet/fabric architecture is not something to brag about as a feature - which is what a lot of comments are doing (AMD did it first!). Intel went through this mess because they had to due to yield. It ain't a feature for the customer.