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Comment by baybal2 | Hacker News Reader

Very informative. Basically they have reinvented an FPGA with fixed blocks...

> The idea of a compiler-based software solution embedded in an architecture would theoretically allow the Aptos processor to interpret workload instructions and distribute them across processing resources in such a way that the amount of work being parallelised is as close as possible to the theoretical maximum, whilst taking advantage of having much lesser architectural inefficiencies than instruction-based processors.

Whether there will be an instruction set, or not, you will have to have some kind of convention for the bitstream for the re-programmable logic, and very likely you will re-implement a kind of an instruction to do that with high level of efficiency.

Modern CPUs already all run microcode on some kinds of a programmable fabric in the front-end to give some degree of programmability for how the front-end, and back-end interact.

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The actual hardware details are kind of danced around a lot in both this article and the somewhat more detailed article it links to (https://www.nextplatform.com/2021/07/12/gutting-decades-of-a...).

From what I can tell, it appears to be a mix between a systolic array and Itanium. The systolic array piece is that it's a grid of (near?) identical ALUs that communicate with adjacent ALUs in lieu of registers. But it also seems that there's an instruction stream element as well, something like the function that each ALU is processing changes every clock cycle or few? It definitely sounds like there's some non-spatial component that requires faster reconfiguration times than the FPGA reconfiguration logic.

As for viability, as another commenter points out, GPUs are currently the competitor to beat. And beating them requires either having stellar results in the don't-rewrite-code space or targeting use cases that GPUs don't do well at. The latter cases involve things like divergent branches or irregular/indirect memory accesses, and these cases tend to be handled very poorly by compilers and very well by the standard superscalar architecture anyways.

Not even that.

Xilinx's processors have a VLIW instruction set feeding a SIMD-DSP surrounded by reconfigurable LUTs.

Ascenium will have to try to displace Xilinx's processors, which are clearly aiming at this "systolic processor" like architecture.

https://www.xilinx.com/support/documentation/white_papers/wp...

To be fair DSPs generally tend to be VLIW even without SIMD as seen in this video on the Sega Saturn https://www.youtube.com/watch?v=wU2UoxLtIm8 .

We (I work for ascenium) do operate with a notion of op, in the sense that we specify ALU ops happening at a given location. I'm not sure that the idea we're trying to convey when we say killing the ISA can be easily understood, but it ties together with the fact that we instruct the core in a far more detailed fashion than your typical CPU during compile time.

In short, our machine code (control words) is far more imperative than typical RISC instructions. RISC specifies what should happen, ours specifies the what _and_ the how

Also, I don't think an FPGA is a very good description of what we do, but on the other hand I did use the same analogy to describe what I do when I started working here, so it's not terribly wrong either

Are you hiring (interns)?

We're hiring, but not interns

Gotcha. Thanks for replying.

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