> Chisel is therefore it's "synthesizable subset".

Chisel is not synthesizing Scala. It is just a library implemented in Scala that allows you to create a data structure that describes a circuit.

Something like:

  circuit = Circuit("test")
  module = circuit.module("test")
  in0 = module.input("in0")
  // ...

The one thing Chisel adds on top of an Object hierarchy that describes a circuit is what PL people normally call "syntactic sugar". I.e., Chisel makes constructing this circuit object look more like a Verilog circuit by taking advantage of some nice Scala features. However, in the background, we are just constructing a data structure that represents a circuit, just like in a GUI library you might construct a data structure that describes your widget hierarchy. Chisel is not High Level Synthesis.