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Comment by krylon | Hacker News Reader

AAAAAH! Had I only bothered to finish reading TFA, it would have answered my question:

"Ten years ago, I asked Intel’s smartphone SoC designers why they were relying on DVFS — Dynamic Voltage and Frequency Scaling — to keep Atom’s power consumption competitive rather than big.Little. According to Intel’s architects, DVFS was competitive with what big.Little could deliver when one considered the silicon die space requirements and the overall power savings. That may have been true at the time — Medfield was generally competitive with the midrange Cortex-A9 devices it was intended to compete against — but it doesn’t seem to be true today."

I assume the idea is that if you're using the LITTLE cores, you turn off the big cores entirely (or at least some of them).

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What's stopping you from shutting down cores with the traditional big-only design? I'm looking at per-core power consumption of my AMD 5800H right now, and I can see that it is able to fully shut down up to 7 cores out of 8, bringing down the entire package power consumption as low as 3.8 W.

Rush to idle is a compromise. There are two basic kinds of loads. User responsive and background tasks.

User tasks want to use the rush to idle because it improves responsiveness. Most background tasks don’t really care.

High performance cores trade power efficient for execution speed by using lots of transistors to analyze the code and optimize on the fly (literally a semi-programmable core in itself to run your core faster). In addition, power consumption is linear with clocks in theory, but not at all in practice.

Let’s consider AMD specifically. In order or semi in order cores are much narrower. All the speculation bits go away. The extra load/store complexity (very significant) also disappears because the core simply can’t use it. SMT will also go away. As it adds a ton of duplication, that also reduces size (10% if I remember Intel’s claims from a few years ago). Simple cores get much better performance per watt and per transistor, but at the expense of time. Makes a lot of sense if time isn’t critical.

On desktop, a zen 3 core at 4.5GHz will use around 12w. Dropping frequency just 200MHz will lower power usage per core by almost 2w. (from Anandtech).

In the space of that one core you mention, you could fit 4 complete in order cores with lots of room to spare. They could all run at a couple GHz and still use less than half the 3.8w you mention.

Nothing, but if you need to run tasks then you need to wake these cores up.

If you have low-priority or very short tasks to run, then you can wake just a few small cores, and that's way less expensive than to wake big cores.

An other advantage is that it can help progress background tasks more efficiently: if you run background tasks on small cores then you don't need to suspend tasks which need the big cores or migrate them between threads to run background tasks.

Compared to ARM, Intel has the additional problem that their Atom descendant little cores don't implement the full instruction/feature set of the big cores. That could be because the full set is (power/die-size wise) expensive, or because of market segmentation strategy, but it probably makes an Intel big.LITTLE far less straightforward than ARM.

(https://overclock3d.net/news/cpu_mainboard/intel_s_hybrid_bi...)

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