Hacker News Reader

Comment by lacksconfidence | Hacker News Reader

Perhaps particularly interesting about this approach by AMD is that the typical memory on a CPU die isn't as dense as it can be, because of the processes they have to apply to the wafer to also build the CPU transistors. With AMD moving to separate chips they can use a process that builds denser memory than what is typically seen on a cpu.

View on HN

I would think this helps with yield issues on your new manufacturing node as well.

If you have a 33% yield on one new chiplet that doesn't triple the price per unit for the package.

Yields are normally kept high by having extra device blocks, and achieving a working config by cutting some links on the die with a laser.

Some chips get downgraded in the process: if you can't sell a 4-core CPU with 8MB of L1 cache, you can disable the core that fails tests, and / or disable the parts of the cache that fail tests, and sell a 3-core part with 4MB cache; AMD did just that back in the day.

> Some chips get downgraded in the process: if you can't sell a 4-core CPU with 8MB of L1 cache, you can disable the core that fails tests, and / or disable the parts of the cache that fail tests, and sell a 3-core part with 4MB cache; AMD did just that back in the day.

How does that work anyway? I mean, how is a processor actually tested at the pre-packaging stage, given that you'd need to provide it with power and cooling for a test?

They use a wafer tester that literally has a tiny bed-of-nails array on it that contacts the bumps for a given die on the wafer, and can move over the wafer in x and y. It provides power and test signals, although power is typically quite limited (<100A of current or so). The good die will then go on to get packaged and further tested before being assembled onto a PCB

Camera takes photos and compares with how it should look like.

I'd assume they attach it to the substrate, glue on the IHS (the lid), and run diagnostics on the completed chip. If any issues are detected, the processor would contain functions to disable certain blocks (through JTAG or something).

Hard to really say if it will negatively or positively impact yield.

You should be able to cram in more chips per wafer. But, you might see more of those turn out to be duds due to the more complex layers. This 3d stacking has an amplifying effect to flaws in lower layers.

We'll see if Zen 4 or Zen 5 has 100Mb caches... that'll be the true test.

The proper yield comparison for TSV wouldn't be against the one-chip, less-stuff version, though. It'd be against what you'd have to do to achieve the same capacities without TSV: a multiplication of the number of mask layers per chip, to produce a single extremely "tall" chiplet. That'd be an extremely low-yield process (which is why nobody's doing it.)

Reply on news.ycombinator.com