DSLs really matter in the hardware and digital design space - a space that seems to be completely devoid of innovation when it comes to tooling.
A couple languages that try to bring RTL into the 21st century are nMigen-Python and Chisel-Scala.
I'm currently writing an RTL in Nim.
Nim's macro system allows you to do really cool things like instantiate named RTL wires and create custom operators like `:=` for Signal assignment. Really excited about tier 1 BigNum support coming soon - which will make it easier to simulate arbitrary width integer signal arithmetic.