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Comment by ksec | Hacker News Reader

Tl;dr

V1 = Slightly tweaked ARM Cortex X1 with SVE ( Used on Snapdragon 888 ) on 7nm aiming at ~4W per Core.

N2 = New Cortex with AMRv9, ~40% IPC improvement over N1 or 10% lower than V1, SVE2, 5nm aiming at ~2W per Core. With Similar die size to N1. ( I fully expect Amazon to go 128 Core with their N2 Graviton )

So in case anyone is wondering, no, it is not Apple M1 level. Not anywhere close.

CMN-700 = More Cores and support of Memory partitioning, important for VMs.

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The cores don't serve the same purpose as the M1 cores. M1 is optimized for single thread at the cost of die size (and a bit of power). I don't have exact numbers, but say the apple M1 core takes 1.5x the die area of N2, the you'd get better performance by putting in 1.5x the number of N2 cores.

Yes. M1 / A14 is also a 5W+ Core. So a different set of trade off. I mentioned the M1 because it is the question that always comes up and people keep banging on about it. I wish most tech site would simply point this out since they have the reach. But it is obvious neither Apple nor ARM have the interest for their pieces to be named and compared in this way. And I guess tech site wont do this to harm any relationship.

Nice TLDR!

It's apples and oranges comparison to Apple M1 chips (server vs. consumer) but does hint at what's possible with the next generation ARM Cortex "X2" cores, that could appear in next year's flagship smartphones and laptops. A 30-40% IPC jump, partly due to moving to 5nm fabrication process, is huge.

Given the right implementation, namely squeezing more big cores than the current 1-3-4 configuration, it could close the gap considerably with Apple.

Process node changes generally doesn't do anything for IPC - those are generally rather due to microarchitecture improvements, so I doubt the move to 5nm has anything to do with the IPC gain..?

The node shrink lets you afford more transistors that provide more IPC.

I agree with that - but if you take an unchanged core and manufacture it at a different node, then you won't see a change in IPC, which in my book makes it questionable to attribute IPC gains to the process node.

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