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Comment by nnadams | Hacker News Reader

You are right that CISC processors (like x86) have more capabilities, i.e. more instructions. You as the programmer get to take advantage of the "extra" very specific instructions, so overall you write less instructions.

Less instructions sounds great, but with CISC you do not know how long those instructions will take to execute. RISC has only a handful of instructions, that all take 1 clock cycle (with pipelining). This makes the hardware simple and easy optimize. The instructions you lose can just be implemented in software. That space on chip can be used for more registers and cache, for a huge speed up. Plus nowadays, shared libraries and compilers do a lot of work for us behind the scenes as well. Having tons of instructions on chip only is a benefit for a narrow group of users today.

We've found that for hardware it's better to reduce clock cycles per instruction, rather than reduce total number of instructions.

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> RISC has only a handful of instructions, that all take 1 clock cycle (with pipelining).

This isn't really the case with modern ARM. Fundamentally modern ARM and x86 CPUs are designed very similarly once you get past the instruction decoder. Both 'compile' instructions down to micro-ops that are then executed rather than executing the instruction set directly so the distinctions between the instruction sets themselves don't matter all that much past that point.

The main advantages for ARM come from the decode stage and from larger architectural differences such as relaxed memory ordering requirements.

https://retrocomputing.stackexchange.com/questions/13480/did...

So ARM nowadays is just straightly better than x86?

For the most part I think so. The main advantages x86 has are based on code size. Many common instructions are 1 or 2 bytes so the executable size on x86 can often be smaller (and more instructions can fit in the instruction cache). I'm sure there are tons of other small differences that weigh in but I'm not well versed enough to know of them.

A paper I read a few months ago compared instruction density between a few different ISAs. Thumb was 15% denser and aarch64 was around 15% less dense compared to x86. Unfortunately, mode switching in thumb impacts performance which is why they dropped it.

RISCV compressed instructions are interesting in that they offer the same compact code as thumb, but without the switching penalty (internally, they are expanded in place to normal 32-bit instructions before execution).

If they added some dedicated instructions in place of some fused ones, that density could probably increase even more (I say probably because two 16-bit instructions can equal one 32-bit dedicated instruction in a lot of those cases).

It’ll be interesting to see what happens when they start designing high performance chips in the near future.

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