Some more detailed information here: https://en.wikichip.org/wiki/uc_davis/kilocore
No idea how it has progressed or if sample units became accessible - which would be nice.
No idea how it has progressed or if sample units became accessible - which would be nice.
> The chip is designed as a massively parallel processor array, with 992 cores arranged as a grid 32 by 31. Eight additional cores are found along with 12 memory modules of 64 KB SRAM each (for a total of 768 KB). Communication between cores is done via a dual-layer source-synchronous circuit-switched network and a very-small-area packet router (see wormhole routing). The circuit-switched network supports communication between adjacent and distant processors, as resources allow, with each link supporting a maximum rate of 28.5 Gbps. Maximum throughput is 45.5 Gbps per router. Both network types contribute to an array bisection bandwidth of 4.2 Tbps.
24 cores of failure out of 1000 would be an error rate around 2%, which would help in yields.
I had assumed there were 1000 instruction memory SRAMs in there but of course that'd be impossible considering the leakage numbers and there's actually just 12 x 64KB SRAMs shared by all the cores:
Per core
640 bytes (128x40-bit) local instruction memory
512 bytes (256x16-bit) local data memory
768 KB SRAM on-die
12 shared SRAM memory modules, 64 KB each
> Instructions may come from the local instruction memory or they may be fetched from one of the independent memory module
But then goes onto say:
> the KiloCore's processors do not contain traditional caches.
Hopefully their paper has more info.
The survey that the "World’s First 1,000-Processor Chip" claim is based on (http://vcl.ece.ucdavis.edu/misc/many-core.html) doesn't seem to include any network processors, some of which are technically programmable. But even if it had, they wouldn't have found any of the information required for the table and definitely not a datasheet!
Or is the 16 bits CPU too limited for training operations?