FPGAs typically do contain dedicated RAM areas, because implementing it out of FPGA logic slices is terribly inefficient.
FPGAs typically do contain dedicated RAM areas, because implementing it out of FPGA logic slices is terribly inefficient.
(* ram_style = "distributed" *) reg [data_size-1:0] myram [2**addr_size-1:0];
block: Instructs the tool to infer RAMB type components.
distributed: Instructs the tool to infer the LUT RAMs.
registers: Instructs the tool to infer registers instead of RAMs.
ultra: Instructs the tool to use the UltraScale+TM URAM primitives.
See: https://www.xilinx.com/support/documentation/sw_manuals/xili...
edit: formatting*
Finding a mentor is very difficult for me unfortunately (from a third world country, and not particularly rich). I will check out the books and research if there are any obsoleted / old parts. Thanks for the heads-up on SystemVerilog.
Thanks again :)