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Comment by antman | Hacker News Reader

Layman here! I see a lot of posts on that subject lately so I need to ask: Can someone design a RAM chip?

Yes, designing ram is a lower level operation as compared to designing logic via an HDL and needs to directly take the process (chemistry, optics, mechanics) of the fab into account.

https://openram.soe.ucsc.edu/

DRAM chips are fascinating.

Instead of going with the much more expensive SRAM, someone decided that refreshing billions of capacitors hundreds of times a second while performing read and write operations is an acceptable way of storing data (even if only while powered).

I wonder what the managers who first heard the idea must've thought :D

And it works so well! It's probably one of the most reliable component in a computer.

Many of the early RAM systems were non-persistent (mercury delay lines, phosphor) and some were destructive-read (core memory).

Appears to have been invented by Dennard of Dennard Scaling: https://www.thoughtco.com/who-invented-the-intel-1103-dram-c...

What do you mean specifically by "design a RAM chip"? (obviously RAM chips that you can buy are designed before they are made, so that's probably not what you are after?)

FPGAs typically do contain dedicated RAM areas, because implementing it out of FPGA logic slices is terribly inefficient.

FPGA designer here. Just wanted to point out that “efficiency” is highly context sensitive in FPGA design. Everything is an area / speed / power trade-off. If you only need a ram that is 8-bits wide and 64 words deep then it might be way inefficient to waste a dedicated 18kbit block ram on it when it would fit better into 2 LUTs. This is why Xilinx, for one, provides pragma such as RAM_STYLE to help guide synthesis:

(* ram_style = "distributed" *) reg [data_size-1:0] myram [2**addr_size-1:0];

block: Instructs the tool to infer RAMB type components.

distributed: Instructs the tool to infer the LUT RAMs.

registers: Instructs the tool to infer registers instead of RAMs.

ultra: Instructs the tool to use the UltraScale+TM URAM primitives.

See: https://www.xilinx.com/support/documentation/sw_manuals/xili...

edit: formatting*

Hey there, sorry for going off topic, but as a FPGA designer, are there any learning resources you would particularly recommend for someone starting with FPGAs by themselves? With the goal of learning more about computer architecture and the way CPUs work on a lower level.

Not off the top of my head. I would definitely recommend trying to find a mentor with current experience rather than getting started by yourself if possible depending on your background. The last time I mentored someone and looked at beginner resources was over 10 years ago and at that time I was recommending beginners with at least some of the requisite college coursework buy and read "The Design Warriors Guide to FPGAs" to get started and then buy and use at least one of Peter J. Ashenden VHDL and Verilog texts as HDL language references. Much of The Design Warriors Guide might still be relevant but I haven't looked at in a while. Ashenden's books are probably still mostly relevant for the versions of the languages they covered, but these days I would try to also find a good book on SystemVerilog. All that is probably overkill towards the goal of learning more about computer architecture and the way CPUs work on a lower level though. For me I found all my undergraduate and graduate coursework, including a class on operating systems, to be essential to my understanding and real world use.

Thank you very much for your reply.

Finding a mentor is very difficult for me unfortunately (from a third world country, and not particularly rich). I will check out the books and research if there are any obsoleted / old parts. Thanks for the heads-up on SystemVerilog.

Thanks again :)

Possibly, but why would you want a less efficient RAM chip that costs more compared to something that's a commodity you can buy?

There’s basically certain little magic sauce to RAM chip design. The production process (which is rather independent from the commonly discussed “node size” production for CPU/GPU-related tech) is where the magic happens.

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