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Comment by robert_foss | Hacker News Reader

migen is a very popular HDL in the Open Source FPGA space.

Robert Baruch on Youtube is building a (relatively simple) RISC-V CPU core using nMigen and it looks like a very nice tool to work with relative to other HDLs I've seen (though I've never had to actually use an HDL myself before so I may not be the best judge). Here's a playlist of the video series, with the earlier videos basically being an introduction to nMigen: https://www.youtube.com/watch?v=YgXJf8c5PLo&list=PLEeZWGE3Pw... His use-case is a bit unusual in that his ultimate target is discrete ICs instead of an FPGA, but he's using it to do formal verification of his core before he commits the time to building the schematics and laying out the PCBs.

At best, it's like the fourth or fifth most popular language among hobbyists not looking to tape out their designs (is there a single nMigen design that's been taped out?).

This would be be (by orders of magnitude?) the most complex design attempted in the language, which pushes it into NIH territory.

ours will be one of the first or second. Staf from Chips4Makers will be using nmigen-based infrastructure. the nice thing about being charitably-funded to do research is: it's not our personal money. NLnet has offered to pay for a 180nm tape-out, and we also qualify for Google-Skywater 130nm.

also, you may be interested to know: Sorbonne University has access to Cadence. after converting to Verilog, they ran our 180nm design through DRC and it passed 100%.

nmigen has some deterministic behavioural guarantees and much more which make it a far better choice. it happens to output Verilog which we can treat as a (readable) machine-code (assembler-like) intermediary.

My concern with nmigen with a taped out design isn't that you can get it to pass the PDK rules. It's the difficulty in creating a productive feedback cycle once simulation shows the inevitable bottlenecks in your design for each process node you're targeting.

It's for sure a solvable problem, but 9 time out of 10 the FOSS developers trying to push a new language into this space end up not meeting their actual "release a usable design" goals but instead spend all their time yak shaving the language. It's a classic nerd snipe in the space.

luckily, through yosys, conversion to Verilog is trivial. and yes, when we get to 22nm (etc) we'll need to license commercial tools from Cadence, Synopsis etc. we're setting up a commercial operation to do that.

right now we're in like "R&D mode", thankfully paid-for by NLnet.

i go into some detail about why we chose nmigen, and what can be done with it. it was not a "light decision", it was several months comprehensive review.

here's the point in the FOSDEM talk i just did: https://youtu.be/7rCeNzrCB_g?t=1939

Can you point to 3 instances of this happening?

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