What is the benefit of smaller transistors? Serious question. Why does it matter if I have 7nm vs. 5nm vs. anything else?
Shrinking isn't always a walk in the park though. Some nodes ago subthreshold leakage became a big problem until they figured out how to solve it.
Smaller dimensions means you can set a smaller length for the wire.
As you can see on the diagram on this article, there is a large push into increasing the height of the transistors. That has being going on for more than a decade.
About the width, a finer process means you can keep the width of the most critical transistors the same, but can also trade it off into less width (and performance) where it is less important.
So, overall, smaller dimensions leads to lower resistances. You can trade some of the gain for density, but you'll always get some lower resistance.
Smaller distance -> lower capacitance -> higher clocks
If your chip is too large it can even make it practically impossible to manufacture at scale due to the increased chance of defects as your chip size increases.
It's not the speed of light [in a vacuum], but electric signal propagation speed in copper.
No, it's not. If it were, you'd have photons moving through your copper wire, which would be quite the sensation!
A moving electron does create a change in the electromagnetic field, however, so maybe that's where your confusion stems from?
[0] https://en.m.wikipedia.org/wiki/Speed_of_electricity
[1] http://www.wolframalpha.com/input/?i=c%2F5ghz
Edit: if the chips were much larger. Smaller chips can go faster without becoming antennae.
So? That means that the speed of light is an upper bound, but it's not a bottle neck.
If something oscillates at 1 GHz, 15 cm down the wire the phase is opposite. To me it's perfectly correct to say that speed of light affects the design a lot and in many places probably is a bottleneck.
But electrical signals do.
[1] https://www.intel.com/content/www/us/en/history/museum-story... [2] https://www.apple.com/newsroom/2020/11/apple-unleashes-m1/
Smaller devices use less power so less heat and longer battery life.
Smaller devices mean a smaller chip which is cheaper (although mask costs will be more expensive) or use the extra area for more features like more cache or another processor core.
To Oversimplify.
With a Fixed Yield, and an exact 100% increase in Transistor Density that translate to 50% smaller Die Size.
On a Wafer, that would equate to Double the amount Die you have. All of a sudden your profits increase dramatically.
5nm also have a better power curve so within the same clock speed you have lower energy usage. Hence you can push for higher performance if needed.
The first point of Uni Economics is important for the industry. If you have high enough volume, say hundreds Million of chips per year then it make sense to move to the next node for cost saving. If you have small volume or low margin chip then the Design Cost, which is the most expensive part of chip making, would not work to your benefits.
And it also depends on Wafer price, If 5nm is Double the Price of 7nm then in the above example your unit cost would be exactly the same.
The second point is important for CPUs, and other things that are increasingly computational expensive like WiFi 6 and 5G Modem. You want your Smartphone to last longer on battery so they work better on an energy efficient node.
So basically it is a Cost / Performance trade offs.
If you CPU is 100mm across, the speed of light limits it to 3GHz because that's how many times you can cross the cpu travelling at c. At 10mm you get 30GHz.
100mm across is 10cm, 0.1m, 4 inches. That’s palm-sized CPU - far from any modern silicon.
Theres always this trade off between complexity and speed. Making the components smaller means you can have both!
Seems like an intriguing napkin math limit/simplification though, I'd be interested if anyone could elaborate on if there's any substance to it.
Clock distribution networks use local clocks to buffer and amplify the global clock but they take a significant amount of chip area and make the chip larger. Clock distribution circuitry draws a significant amount of power. It can be 30-40% of the power usage. You want to use them as little as possible.
When designing chips or doing layout for FPGA designs, we do something called timing analysis to find out if signals get to where they should do such that the chip is stable ("meets timing").
There is a lot more to it than just distance. The transistors have speeds, to start with.
That and just because this size gives a bound on how quickly you can do things, the transistor count is also increasing, so the actual clock doesn't increase all that much.