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Comment by EE84M3i | Hacker News Reader

Realistically, how easy is it for Intel to switch like this? Is there really some industry standard interchange format they can use to ship their i3 design off to a different fab? I would have expected them to use proprietary formats from top to bottom.

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Whilst you can easily point your synthesis tool at a new cell library (this is the tool that takes the hardware description in a language like Verilog and produces a circuit that implements it) there is significant back-end work in getting the best out of any library.

Intel will probably have to rework their layouts, deal with new memory compilers that have produce memories with different characteristics and adapt memory interfaces that what they need. Their implementation engineers will take time to understand all of the new design rules, quirks and best optimisation strategies that come with an entirely new library (given this is an entirely different fab there could be significant differences).

I suspect that's why they're going for Core i3 first, they can get away without lots of detailed work and optimisation to really push the process. A straight-forward (ish) port what you've got and see how it goes will be good enough and will give their implementation engineers experience with the new library that they can then use to work on the higher end.

It's not as bad as you think. From a high-level: Modern Synthesis tools turn your RTL code (which is coded in an HDL or Hardware Description Language) into gates, and then map them to a library of "Standard Cells". These foundry-specific cells are physical plans for an AND, OR, XOR, gates, flip-flops, etc. Once the code is mapped to these cells they are run through a Place&Route tool, which lays out all the mapped standard cells onto a plane, and then wires them together in 3D following a set of design rules from whatever foundry you are using. Finally after verifying the physical properties of the output design, you ship it to your foundry using a industry standard format called "GDS2" which is basically a series of 2D layers for turning into actual lithography masks. Doing this process (commonly called "RTL to GDS2") is non-trivial, but could be done to target a new foundry in <6 months. Now, Intel is known to use some custom layout methods rather than this Synthesized flow I've described, but that's pretty out of vogue and is a vestige of their early days.

At a high level, Verilog, a widely used hardware description language, is portable to almost any fab.

There will be all kinds of layouts for specific subcomponents which are harder to move between providers, but I would guess that the move from 14nm Intel to 5nm TSMC will more than outweigh all the layout based optimizations.

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