Reticle limited on Samsung 8nm means plenty of room is available on TSMC 5nm.

Also, GDDR does not have appreciably higher latencies than DDR memory when measured in nanoseconds. It's just more expensive than DDR and much more limited in terms of capacity.

If Apple does go the "huge SoC" route I'd expect to see HBM2 memory with socketed DDR4 or DDR5. It'd provide the best of both worlds - extremely high bandwidth and low latency for a small portion (say 32-64GB) of the memory, and high capacity for the rest (say 1-2TB), all without compromising the unified memory concept.

This is not without precedent - recent Xeon Phis, for all their other shortcomings, have had a similar memory hierarchy.