Just read "Why Is Apple’s M1 Chip So Fast?" [1] to answer most of these questions.
I’ll just hit the obviously erroneous issues here.
A M1 chip has 16 billion transistors for 8 cores. AMD's EPYC Rome has 39.54 billion transistors for 64 cores.
It doesn't make sense to compare the M1 with the EPYC Rome. They couldn't more different and were developed for dramatically different use cases.
(I also don't think it's not a good look when folks feel compelled to state Apple's M1 isn't as fast as AMD's $4000 64-core processor, as if this means anything. Of course the EPYC Rome is faster--duh. Anyways…)
16 billion transistors on the M1 SoC (emphasis on system) gets you an 8-core GPU, a 16-core Neural Processor, a Digital Signal Processor, a Secure Enclave, image processing unit, video encoder/decoder and of course 8 CPU cores and 8 or 16 Gb of memory.
Instruction decoders deal with the out of order execution of the instructions; more decoders enables you to have more instructions "in flight" as they say for the execution cores to run in parallel.
Again, you should read the article for the details, but due to the legacy architecture and technical debt of a 40 year-old instruction set, not to mention with instructions ranging in size from 1 to 15 bytes, it's not easy for the decoders to juggle all of the instructions to do out of order execution of instructions. Yes, even the EPYC Rome only has 4 instruction decoders.
Meanwhile, the instructions for Apple's Firestorm cores are all the same size, making decoding the instructions much easier and faster; so much so that the M1 has 8 decoders, which is unheard of in a mainstream processor.
Here's the bottom line quote from the article:
"In fact, adding more causes so many other problems that four decoders according to AMD itself is basically an upper limit for how far they can go.
This is what allows the M1 Firestorm cores to essentially process twice as many instructions as AMD and Intel CPUs at the same clock frequency."
Apple and AMD solved the "get as many instructions in the pipeline as possible and process them as quickly as possible" problem two different ways.
AMD does it with threading and many cores; Apple does it by increasing the number of instruction decoders and by having 60+ Gb/s bandwidth with a 128-bit bus. Apple didn't implement SMT because they don't need it; they have no issues with keeping their instruction pipeline full.
Bottom line: Apple's approach has more headroom than AMD's approach. They can't add more instruction decoders, so they crank up the clock speed and the threads to execute more instructions per clock cycle. But the M1 is so efficient, it processes twice as many instructions at the same clock frequency.
The M1 runs at 3.2 GHz; it's got a higher ceiling because Apple can add more cores and increase the clock speed a lot before it gets anywhere near the power consumption and other physical limits that AMD is starting to run up against.
[1]: https://debugger.medium.com/why-is-apples-m1-chip-so-fast-32...