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Comment by runeks | Hacker News Reader

> TSMC reckons its 3nm node will pack in somewhere north of 250 million transistors per square millimetre of silicon [...]

> TSMC is already producing chips for Apple’s iPhones on its new 5nm node, which is good for 173 million transistors per square millimetre [...]

3nm™: a transistor is 1 / 250e6 = 4e-9 square millimeters, which is sqrt(4e-9) = 63.2 nanometers by nanometers.

5nm™: a transistor is 1 / 173e6 = 5.78e-9 square millimeters, which is sqrt(5.78e-9) = 76.0 by 76.0 nanometers.

So is it reasonable to say that 3nm™ -- compared to 5nm™ -- is closer to 63.2 / 76.0 * 5 (nm™) = ~4.16nm™? Ie. a reduction in feature size of ~17%?

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3nm, 5nm, 7nm are all marketing names now since the fabs switched to 3D transistors and not a measure of any exact feature size.

When examined via electron microscope, TSMC's 7nm is just slightly denser than Intel's 14nm++ and not half the size.

“You need to understand that this naming scheme reflects only the process. It’s just the process called 14nm or 7nm … It could be called Intel Blueberry Construction 5 or if it is called AMD Strawberry Process 3, it would give you the same amount of information as having 14nm or 7nm (in the name).”

https://www.time24.news/2020/09/der8auer-compares-tsmcs-7nm-...

They appear to already be acknowledging that fact by using the trademark symbol.

I once read a 350 micron CMOS spec of about 100 pages. Probably just a subset of the spec. Detailing the hundreds of different feature sizes. There is no way you can compact that into a single three digit number only describing the smallest feature size of the gate. I believe it has been regarded as naming/marketing for decades, but the future is not evenly distributed. It used to be indicative of density and denard scaling, but now physics and geometry is more complicated and other factors distorts that relation to such a degree that there is soon more noice than signal in communicating minimum feature size.

They are adding more layers. But nobody said there are no other improvements.

Up to 30% power reduction, up to 70% logic density gain, and up to 15% performance gain is all that matters.

> […] up to 70% logic density gain […]

What does this figure reflect when transistor density has only increased by ~45%?

That's a good point. Maybe that's the product of improved transistor density and power efficiency?

I remember seeing someone saying that some of the improvements AMD had with Zen 3 were due to optimization of their layout, so this could be similar.

>up to 70% logic density gain

The keyword here is logic density. Transistor density could refer to many things, in marketing speaks that normally means SRAM.

Why is logic density greater than e.g. SRAM density?

A better measurement would be million transistors per square milimeter(Mtr/mm2).

So Intel's self reported 44Mtr/mm2 @ 14nm, and 100Mtr/mm2 @ 10nm(but currently 10nm is having problems).

Comparing this to Tsmc's 170Mtr/mm2 @ 7nm and 250Mtr/mm2 @ 5nm - is a pretty valid comparison, I think.

So if anything, a naive 'nm' comparison is actually too favorable to Intel? That's amusing, since I've heard it suggested by Intel fanboys that it was the other way around.

Because your parent got it mixed up.

170 Mtr/mm2 refers to 5nm. TSMC's 7nm is roughly 100 Mtr/mm2 depending which 7nm you are referring to as TSMC has quite a few variants.

So yes, Intel's 10nm is roughly speaking the same as TSMC's 7nm.

Just to give another perspective, by the end of 2020, TSMC would have shipped more 5nm wafers then Intel's 10nm has ever shipped.

3D transistors so cubic milimeter might be better?

The transistors are 3D only in the sense that FinFETs aren't just wires on top of a flat surface of doped silicon. There's still no 3D stacking of one transistor on top of another, and transistor density is still best measured by how much 2D wafer area is occupied by a transistor.

This is very different from the situation for NAND flash memory, where the memory cell array is genuinely 3D and pushing toward hundreds of layers of memory cells, so volumetric measurements are starting to become useful. (However, the horizontal dimensions of various 3D NAND designs are roughly similar, so comparing simply in terms of layer count is a good first approximation of bit density.)

Why aren't we stacking layers of transistors in CPUs? Is it because of heat dissipation issues?

Yes, but another reason is that in flash only tiny amount of cells are active at time. So even with much bigger cells that are required for reliable 3D stacking and more heat production per cell it is still very ok.

we are starting to and beginning to stack transistors on top of each other. It is a heat dissipation issue but it seems like we will be done.

What really matters is energy efficiency (watts/transistor or watts/some computation that utilizes the chip well)

Interesting but what is the Mtr/mm2 for a "true" 3nm transistor? How big is the gap with the marketing names?

You can run the math yourself, but its 111,111 Mtr/mm2.

That's doesn't make sense: TSMC 5nm has 170 Mtr/mm2 so TSMC 5nm is smaller than true 3nm? No way.

111,111 MTr/mm2 >> 170 MTr/mm2

My bad, as a non native English reader I read 111.111 Okay so the gap is a x100 :0

The reality is that not all transistors are the same size. They vary in size depending it's exact purpose and how many other transistors it's driving. To the point where they can be up to macro size visible with the human eye in audio switching equipment for example.

What I don’t understand is why Intel don’t just rename their 7nm process to 2nm... or swap to a more favourable metric name.

They are being honest and should be appraised for doing so.

Intel actually did the opposite, and renamed their second attempt at a 10nm process as "10nm" and dubbed the next iterative refinement of that as "10nm+". They're trying to pretend the failed 10nm process used for Cannonlake never happened.

And to some extent, their continual promises to investors that "10nm" and "7nm" were on track force them to actually ship something under those names.

I had the same question recently, for more details:

https://old.reddit.com/r/ECE/comments/jxb806/how_big_are_tra...

The name is supposed to line up with the smallest feature size. The layout of individual transistors and the layout between transistors is not going to be the same for different processes. What customers actually want is high transistor density and low leakage current. That isn’t how new processes are marketed though. They’re marketed as the smallest feature, which does not have a linear relationship with performance metrics.

Yes, that would be reasonable, for generic transistors. TSMC has started breaking out different 'shrinks' for different things, so 'logic' (which is typically gates and flipflops) has one amount, 'ram' (which is typically a gate and a capacitor) has another different amount, and pin drivers often have still another amount.

TSMC talks about SRAM, not RAM. Those are typically 6 or 8 transistors per bit.

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