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Comment by kens | Hacker News Reader

Author here for all your vintage DRAM questions :-)

Great! Question: When 64K DRAM first appeared, I remember a cover article in EDN(?) claiming that nothing denser could ever be built, because cosmic radiation would zap individual electrons, and thus flip bits too frequently, and there was nothing you could do to protect from it. So, how was that thinking wrong?

They discovered that most of the DRAM soft errors were due to alpha particles from the ceramic packaging. Changing the packaging solved most of the problem.

There are still bit flips due to cosmic rays but the rate is low enough that most people don't care. ECC memory can be used if errors are a problem.

More details on Wikipedia: https://en.wikipedia.org/wiki/Soft_error#Alpha_particles_fro...

Some of Sun's servers famously suffered big reliability problems due to using IBM SRAM as caches, which is said to have had elevated error rates due to more alpha-emitting contaminants in their particular package filler.

I was at Sun at the time (although not working on that), and these memory errors were a catastrophic problem for Sun. Customers were paying a lot of money for Sun's reliability and then systems started mysteriously having problems and Sun couldn't figure out why.

I was there too. That would be the ecache problem, right?

I was in the service division at the time, and yes, it was a serious issue. However, if I recall correctly it was limited to the E10K. It was the flagship machine, so of course it got all the attention, but most customers didn't suffer from it.

At least they weren't due to radioactive cows: https://www.jakepoz.com/debugging-behind-the-iron-curtain/

Just wanted to say that is an amazing write up. My first computer was an Interact with 16K of memory built with these chips. I never knew how complex they really are until today. I knew the row/column multiplexing was a PITA for system designers, but was it really worth it? How much more did a package with 7 or 8 more pins cost back then? I guess that's x8 for a system though.

Anyway I hope someplace archives these documentary articles!

I don't know how much more the larger packages cost, but it was enough that Intel really really didn't want to move off 16-pin packages, which caused problems for the 4004 and 8008 processors. In addition, the larger packages took up more space on the circuit board which was a serious disadvantage, especially when you had a board full of memory chips.

I'm so glad to see you tackle a DRAM since it's probably the one main component of a computer that is least understood since it is somewhat analog. Is dummy cell an official term? It's perfectly fine but I thought it might be better described as a reference cell. I enjoy seeing self correcting designs like this. My question would be - if you were to contrast to modern DRAM is it quite similar or what are the differences? (I saw your chart at the end but I'm guessing that there is more similar than different in a modern DRAM?)

Dummy cell is the term used in the paper "Storage Array and Sense/Refresh Circuit for Single-Transistor Memory Cells" that introduced the idea. It's also the term used on the MK4116 datasheet and elsewhere.

The capacitors in modern DRAMs are deep trenches, rather than a simple polysilicon plate. The trenches are 3.6 micrometers deep while the feature size is 45 nanometers, so they are remarkably deep. See the photos here: https://chipworksrealchips.blogspot.com/2014/02/intels-e-dra...

From your new found knowledge of the 4116, do you have any insight into why the 4116 have a reputation for failure? They are often wholesale replaced with 4164 in old equipment.

I don't know anything specific about 4116 reliability problems. But it makes sense that the 4164 would be a few years more modern and thus more reliable.

Very interesting article, and a good topic.

Any idea how big the design team was? I would expect at least two but can imagine up to twenty people.

And wonder if the masks were manually prepped.

The Computer History Museum has on exhibit a rubylith mask for the 4K DRAM chip. According to the designer's oral history, they started using a Calcomp plotter to cut the rubyliths for the 4K DRAM while earlier ones were hand-cut.

It wouldn't have been possible to make the masks for the 4K chip by hand because hand-cut masks wouldn't be accurate enough. The problem was that the sense amps need to distinguish tiny voltage differences. If you cut the sense lines by hand, they would be slightly different widths, enough to mess up the signals.

The conference paper on this memory chip was authored by Schroeder and Proebsting of Mostek, so there were two main designers. There must have been more people on the team, but I couldn't find the size.

https://www.computerhistory.org/revolution/digital-logic/12/...

https://www.cs.utexas.edu/~hunt/class/2016-spring/cs350c/doc...

Interesting. I did some (IT) work for a company making photo plotters for the PCB industry. The MDA Fire 9000, later Cymbolic Sciences and other companies. This was about 1985.

They had a minicomputer with a hardware rasterizer driving a laser writing to photosensitive film. They had amazing throughput for the day.

One of the issues was temperature and humidity stability of the film. It would change dimensions with as little as 10% change in humidity.

The change was more than the resolution of the laser.

We had soviet clones of this chip. Part numbers КМ581РУ4/КМ584РУ4/КМ565РУ3 (MK4116-2/MK4116-4)

Would love to see kens reverse engineering those to find out if they were direct copies or something else.

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