Reverse-engineering the classic MK4116 16-kilobit DRAM chip

I don't think Apple were the only ones to do this, but it is very clever.

Thanks for your kind comment

Great! Question: When 64K DRAM first appeared, I remember a cover article in EDN(?) claiming that nothing denser could ever be built, because cosmic radiation would zap individual electrons, and thus flip bits too frequently, and there was nothing you could do to protect from it. So, how was that thinking wrong?

I'm so glad to see you tackle a DRAM since it's probably the one main component of a computer that is least understood since it is somewhat analog. Is dummy cell an official term? It's perfectly fine but I thought it might be better described as a reference cell. I enjoy seeing self correcting designs like this. My question would be - if you were to contrast to modern DRAM is it quite similar or what are the differences? (I saw your chart at the end but I'm guessing that there is more similar than different in a modern DRAM?)

Just wanted to say that is an amazing write up. My first computer was an Interact with 16K of memory built with these chips. I never knew how complex they really are until today. I knew the row/column multiplexing was a PITA for system designers, but was it really worth it? How much more did a package with 7 or 8 more pins cost back then? I guess that's x8 for a system though.

Anyway I hope someplace archives these documentary articles!

From your new found knowledge of the 4116, do you have any insight into why the 4116 have a reputation for failure? They are often wholesale replaced with 4164 in old equipment.

We had soviet clones of this chip. Part numbers КМ581РУ4/КМ584РУ4/КМ565РУ3 (MK4116-2/MK4116-4)

Very interesting article, and a good topic.

Any idea how big the design team was? I would expect at least two but can imagine up to twenty people.

And wonder if the masks were manually prepped.

That's what flash memory does, it can store four bits per cell (quad-level-cell) https://en.wikipedia.org/wiki/Multi-level_cell

The Intel 8087 math coprocessor stored two bits per transistor in its microcode ROM. It used four transistor sizes / voltage levels. This was necessary to fit the microcode on the die. https://www.righto.com/2018/09/two-bits-per-transistor-high-...

It just comes down to noise. If you can detect X levels successfully 1 out of 1x10^Y times, then you can ship it. Just set X and Y to whatever your specs should be.

Therefore the memory controller had to keep track of when & what was accessed?

It was much more simple than that.

A typical DRAM of the era had 128 rows (at least as externally visible; what's inside is up to the DRAM implementer).

So in a higher end system the memory controller, about every 15 microseconds, would increment a 7-bit binary counter. It then would command all the DRAMs to simultaneously do a refresh cycle with this specific row address. This refresh took priority over normal read and write.

No need to optimize refresh by skipping it for rows which had recently been accessed. Just blindly refresh all 128 rows in sequence.

Internally a 16k bit DRAM would have 128 rows and 128 columns. Each time a row is read, all 128 associated columns are read in parallel. Then the contents of the selected single column are output. That's what makes refresh work without consuming too much of the chips bandwidth. A refresh of a row results in all 128 columns of that row being refreshed.

It takes about 2000 microseconds to do 128 refreshes. That's often what the DRAM chip was specified for. In reality the chips could often retain content for a minute at room temperature. It was when operating at the limit of 70C that refresh every 2 milliseconds became close to necessary.

Some microprocessors of the era, such as the Z80, had an internal 7 bit counter. The Z80 could be easily set up to send this 7-bit counter out to the DRAM after every instruction fetch.

So a Z80 system did something like this:

   fetch an 8-bit opcode
   refresh the next 1 of 128 rows of DRAM
   fetch additional instruction bytes
   complete the instruction

Since a Z80 operated at about 2 MHz minimum and instructions completed in about 6 cycles, DRAM memory was being refeshed, once per instruction, at a much faster rate than the chips needed. There was no such thing as slow divide instructions. The worst case IIRC was about 12 or so cycles to complete an instruction.

The only downside to this sort of refresh is in systems that have more than one word width's worth of chips. A normal read or write accessed a single word. Simple refresh accessed all DRAM chips in parallel. Much higher power consumption.

So, e.g. 16 K bytes of memory needed 8 DRAM chips. Whereas 64 K bytes of memory needed 32 DRAM chips. In a Z80 system, which read 8 bits at a time, only 8 chips would be active during normal read/write but all 32 chips would be active in refresh.

A DRAM chip that was idle consumed a few mW of power whereas a DRAM chip that was being accessed or refreshed consumed a few hundred mW of power. So in a large system (hundreds of chips) you couldn't take as simplistic an approach to refresh as the Z80 did.