If you do address multiplexing the obvious way, it will slow down your memory cycle since you need two steps to load the address. The solution in the MK4096 memory chip was you first load the row address and the memory chip starts accessing the row of 64 bits. While that is happening, you load in the column address. That should be loaded at about the same time the 64 bits are ready to select. The column address then selects the one bit you want out of the 64-bit row.

The result is that you can avoid the speed penalty of address multiplexing, but it requires careful timing, latching, and two separate internal clocks.