I posit that much of what we herald as "innovation" is just what you'd naturally come up with if you work on the problem long and hard enough.
It was the invention of tri-state logic that made address multiplexing easy to do.
Yeah, with tri-state logic (high voltage, low-voltage, and high-impedance state), its easy to implement. But before the high-impedance state was formalized, its less obvious how you're supposed to hook up multiple chips onto a single address + data bus.
Someone had to invent "Chip Select", as well as how the transistors, voltages, and currents flow under such conditions. Its certainly easy to "reinvent" after you've been introduced to the concept, but it probably wasn't easy to think up first.
Another common approach was the open-collector bus, for example in the Xerox Alto. The gates connected to the bus could pull the bus low but not high. Pull-up resistors pulled the bus high. In some cases, multiple devices would deliberately talk to the bus at the same time, OR-ing together their values. The downside of an open-collector bus is it's relatively slow to transition high, since you have a low-current resistor pulling it high. Tri-state drivers, on the other hand, can provide a solid current both high and low.
(TRI-STATE is a registered trademark of National Semiconductor, interestingly enough.)
Ah right, and that's still used by I2C if I remember correctly (a low speed bus that's surprisingly common).
I didn't know about IBM's AND-OR bus before. But now that I think of it, the open-collector bus is the exact opposite of AND-OR.
Open-collector is common today because modern chips (CMOS) can sink more current than they can source. I don't know if TTL (or whatever IBM Mainframes used back then) had different characteristics which made the positive-variation more useful.
FWIW, even the 4004 (1971, predating the MK4096 by three years) used multiplexing and I'm sure it was a known approach prior to that.
You're right in this instance.
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The innovation therefore, was coming out with a 16-pin RAM chip when everyone else was coming out with 22-pin RAM chips.
Looking up the history of the time, Intel, and other big companies, were betting on 22-pin RAM chips to deal with the addressing issue.
The innovation was realizing that you're strobing RAS (Row Address) and CAS (Column Address) in separate cycles anyway. By using those separate cycles, you only needed 6-pins to address, even on bog-standard address busses.
Sure, the Intel chip may have a 16-bit address bus, but the MK4096 didn't care. Wire up the bottom 12-bits, 2-pins to each input address pin, and you're set. Seems brilliant to me.
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I keep looking at the datasheet and the main thing that annoys me is that its wasteful TTL. But I guess that was the late 60s / early 70s for ya, CMOS wasn't invented yet so I guess TTL was what they used.
The fundamental chase of bandwidth-per-pin hasn't stopped. Two recent examples: Eton RPC DRAM manages to essentially run the whole protocol over the data wires using just 22 pins for a 16-bit DDR bus. Another: GDDR6X finally introduced PAM4 (four voltage levels per pin = double the bandwidth). Now we just need to combine these ideas ...
I've had several projects that resulted in "patent pending" applications that I've had to review. It's frustrating to talk to sales and legal folks who want to sell an innovation as if it were some culinary experience for which we've got not only a secret sauce recipe but also world-class chef skills, when I know it wasn't particularly difficult: I just stood in the kitchen with supermarket ingredients, an average palette, and tried variations until it tasted the way I wanted it to.
I'm not cooking, I'm building automation equipment, but the fact that you couldn't buy something off the shelf to do a particular task before my efforts was primarily because the application wasn't common enough yet to make it a commodity, not that it was an insurmountable obstacle that I miraculously overcame.
He has some point tho.
The result is that you can avoid the speed penalty of address multiplexing, but it requires careful timing, latching, and two separate internal clocks.
>just what you'd naturally come up with if you work on the problem long and hard enough
yes, there are systematic approaches to generate inventions (especially if we use the truly low bar of "patentable" :). Even more, if you look at Einstein and the rest of 20th century science following his methodology, i think there is a systematic approach to making discoveries too. And i suspect that "epiphanies" happen mostly to somebody who worked on the problem long and hard enough. Even "epiphaneous" graphene discovery i think was really a result of the long chain of senselessly looking experiments like levitating a frog (an Ig Noble winner).