> Didn't IBM have an ALU design that were more harden again calculation errors?
I'm genuinely confused what is meant by this in practice. Like some sort of redundant ALU architecture or rad hard encapsulation?
I'm genuinely confused what is meant by this in practice. Like some sort of redundant ALU architecture or rad hard encapsulation?
this might be what is referenced?
I did work as a CPU logic desiger at Amdahl. We had full parity through-checking, so an ALU intermittent logic error would raise a parity exception. Certainly IBM would have had the same, it was standard SOTA reliability logic for the era of mainframes when I was a designer.