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Comment by rckoepke | Hacker News Reader

Some people predict that feature shrinking may end around 2025 with an inability to go below 2nm. If that's the case, Intel (and everyone else) will get time to "catch up" to the latest technology standards around 2030. TSMC may not be able to hold a lead forever, if there is a physics wall that stops additional shrinking.

There will be additional efficiencies to be found, and TSMC may continue to have an edge on a business-process level, but if shrinking stops, I'd expect the market to become as competitive as vehicle manufacturing currently is, by 2040.

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TSMC has a current roadmap of Gate All Around 2nm in 2024 ( 3nm GAA in 2022 is increasingly uncertain ), 1.4nm Nanosheet in 2026 and 1nm in 2028. And this isn't just TSMC, Intel CTO just came out yday with similar timeline. Basically the whole industry is moving to GAA and Nanosheet. Anything too far beyond is unknown. But the last conference TSMC has pointed out to having some ideas for 0.7nm in 2030.

So I think everything is good til 2030.

Comments like this are why I love HN, I didn’t know anyone was considering sub-nm in anything beyond a random though, that is quite astounding.

Engineering in the billionths of a mm, alien technology to anyone born when I was born in 1980.

The smallest half-adder is just a double fistful of atoms — about a million times smaller than the proposed 2nm GAA logic. The doubling rate is going to slow down, so we’re talking ~20 generations of at least 3+ years, or more. Who the hell knows what things will look like in the year 2100.

A single silicon atom is 0.2nm... Where are these extra orders of magnitude coming from?

Transistors have been manufactured as a 3D structure for more than a decade and they have multiple dimensions. The idea behind process node naming was primarily about how big a planar transistor would have to be to provide the same transistor density. However, since vendors can slap whatever label they want on their process that's what they end up doing.

If you want to compare manufacturing processes then simply compare transistor densities. That way you will avoid the paradox of thinking that the physical limitations of an old transistor design apply to a chip that is using a completely different design. Here is a list of different possible designs [0].

[0] https://www.extremetech.com/wp-content/uploads/2019/05/FET-T...

Minor nit: billionth of a meter, not of a millimeter.

iPad On-screen keyboard strikes again I'm afraid.

2040 is in 20 years. With mainland China now investing massively in this the competition will be intense no matter what and that's probably the greater long term threat to TSMC.

TSMC did not exist 33 years ago, so 20 years is a very long time especially with the full weight of the Chinese government thrown in.

According to this article https://semiengineering.com/china-speeds-up-advanced-chip-de... they are into advanced chip development:

-SMIC is shipping 14nm finFETs, with a 7nm-like process in R&D. -Yangtze Memory Technologies (YMTC) recently entered the 3D NAND market with a 64-layer device. A 128-layer technology is in R&D. -ChangXin Memory Technology (CXMT) is shipping its first product, a 19nm DRAM line. -China is expanding into compound semis, including gallium nitride (GaN) and silicon carbide (SiC). -China’s OSATs are developing more advanced packages.

People should look at cellular.

About 20 years ago China started developing its own 3G flavour as a way to develop its technology and to catch up. People were saying that they were quite far behind and that this might only sell in China (which it mostly did).

But today we see the result of this long term investment with Chinese companies front and centre in cellular an 5G.

I feel that chip manufacturing has shot up to an even higher priority for them now, so I'm thinking that the landscape may look very different from now in 20 years...

TSMC doesn't have to hold a lead forever, they just have to win long enough to cripple Intel's R&D income.

> if there is a physics wall that stops additional shrinking.

There are really a lot of density boosters on the table to move the industry to N1 without much actual physical scaling.

Buried metal, CMOS-on-MOS, cells micro-optimisation, high-k on more things, vertical GAA...

If they can get to 0.5 na on 3500, then you don't even need to double pattern to reach N1 with all of the above

What is N1?

I believe N# are names of various process nodes. Shorthand, people refer to something as the "5nm node" but really there may be multiple (processes | nodes | technology nodes | process nodes | process technologies) that are "5nm".

wikichip has five nodes listed under "5 nm lithography process", two of which are TSMC's:

- N5

- N5P

so N1 would be a hypothetical future process that can produce '1nm' "features".

Intel's roadmap (from last year) is suspected to target 1.4nm in 2029

https://www.anandtech.com/show/15217/intels-manufacturing-ro...

Given that Intel seems second only to Elon Musk in missing target dates, what does that translate to? 2050?

Hopefully the gravy train of technology doesn't end before I enter retirement.

And their previous roadmaps were completely inaccurate in the most recent shrinks which saw shrinks take, what, 5 years rather than 1 year? Have they even gone to 7nm successfully yet?

Roadmaps are just speculation at this point.

> feature shrinking may end around 2025 with an inability to go below 2nm

I feel like I've been seeing these "can't shrink further very soon" claims (including the claim of hard, insurmountable physical limits) for about as long as fusion was 20 years away.

around 2025 with an inability to go below 2nm. Such predictions are "wild guess" but I've not yet seen an expert strongly bet in favor of a complexity/cost wall.

If I remember correctly, a silicon atom and the spacing between them make ~0.2 nm If you think that starting at 2nm we are getting closer and closer to this physical limit is utterly wrong: Because what we call 2nm is not a 2nm transistors. Today transistors (7nm) have some parts that are on the hundred of nanometers! What I would like to know is how much reducing those parts will bring performance? Maybe those parts of a transistor actually matters far less?

Isn’t there still a ton of room for improvement with 3D ICs? And of course power/heat will still be quite important as well although heat in particular gets significantly harder with 3D chips (or at least I think)

Also, being the first doesnt mean you necessarilly win: smaller node size will give poorer wafer yields, giving Intel time to milk older node processes while playing catchup with TSMC.

TSMC also has older process nodes running, there's literally no advantage to Intel failing to execute on their product roadmap; it's all downside.

Older and at this point mature 7nm processes which is behind I suspect the new XT processors from AMD, yields improved enough to bin higher.

Intel has been milking those 14nm++++++ processors for so long now that TSMC went screaming past dragging AMD and Apple with them, I'm not seeing an upside for Intel out of any of this and that's before Meltdown.

I'm still smarting about that dropping 3 weeks after we rolled new servers out at work.

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