That being said, I'm not too worried about Intel, they have such a diverse silicon portfolio(FPGAs, Optane, etc.) that I'm sure they'll be fine in the end.
My $0.02.
Now, you have huge entities like AWS that can, for example, move things like ALB, RDS, SQS, or Aurora off of Intel on little more than a whim.
Basically, the leverage on the customer side is consolidated now, and the barrier to leave you is lower.
Whom is Amazon going to sell low-bin Gravitons to? It isn't cost effective to run them, just like it's not cost effective to use low-binned Intel or AMD chips in datacenters. It's intrinsic to the way all chips are manufactured.
Making your own low performance chips makes clear economic sense, as the producer and consumer of all output. But there have been decades of people trying to make their own high-performance chips as both consumer and producer, and they inevitably fail. And it's not super black and white, whose "subsidizing" whom, in the chip business - datacenter purchasers get cheaper chips because Intel can sell lower-binned parts to enthusiasts, while enthusiasts get cheaper parts because datacenters pay more. Same thing is observed for GPUs, product segmentation in chips is a real synergy and not zero sum.
Who knows if that will succeed, for the idiosyncratic reason of the foundry business being separate from the IP business. Did it really just take a corporate reorg? Maybe AMD was right.
But my point on how easy it is now, as compared to the past, for large swaths of customers to move away from Intel, stands. Moving to AMD or some 3rd party ARM provider are options outside of Graviton that can be done quickly.
While I recognized that this is indeed the case, I'd not considered some of the recent plays that Apple has been making. Forget those Gravitons. Forget those low volume datacenter ARM chips too. Also forget those high-binned EYPC and Xeon chips.
What happens when those rackmount Mac Pro machines go to Apple silicon? Datacenters are already paying a premium for processors, but these are much better at performance-per-watt, and Apple can afford to cut the prices on the first and second generation ones to make it up in volume and then ratchet up the prices later once they've got the marketshare.
They'd just run their internal clusters with the high binned parts, and the low binned parts would go into their AWS budget tiers.
Tada! Now they've got the best, and unloaded the rest onto suckers while billing them for the privilege.
And low bin chips are still going to be more power efficient than the previous generation.
The answer is nothing. If it isn't already, TSMC will eventually pass the cost onto Apple.
If they're starting with designs that are very energy/heat efficient then couldn't they fuse off the bad parts of the dies and then glue like 10 of them onto a single interposer and still have a tdp competitive with x86 server parts?
To the same customers as higher-bin Gravitons. It'll just be sold in the form of services, where you don't get to see the CPU directly.
Man, I would not know if amazon was bribing anandtech or something, but the gravitron2s are they're wiping the floor here with Intel and Amd when it comes to performance per cost and even holding their own single threaded which I did not expect.
https://www.anandtech.com/show/15578/cloud-clash-amazon-grav...
Recently TSMC uses names like N7 and N5 for their processes, because they're no more related to actual nanometers on chips. Same for Intel, but they stick to their traditional naming.
There will be additional efficiencies to be found, and TSMC may continue to have an edge on a business-process level, but if shrinking stops, I'd expect the market to become as competitive as vehicle manufacturing currently is, by 2040.
I'm still smarting about that dropping 3 weeks after we rolled new servers out at work.
https://www.anandtech.com/show/15217/intels-manufacturing-ro...
Roadmaps are just speculation at this point.
If I remember correctly, a silicon atom and the spacing between them make ~0.2 nm If you think that starting at 2nm we are getting closer and closer to this physical limit is utterly wrong: Because what we call 2nm is not a 2nm transistors. Today transistors (7nm) have some parts that are on the hundred of nanometers! What I would like to know is how much reducing those parts will bring performance? Maybe those parts of a transistor actually matters far less?
TSMC did not exist 33 years ago, so 20 years is a very long time especially with the full weight of the Chinese government thrown in.
-SMIC is shipping 14nm finFETs, with a 7nm-like process in R&D. -Yangtze Memory Technologies (YMTC) recently entered the 3D NAND market with a 64-layer device. A 128-layer technology is in R&D. -ChangXin Memory Technology (CXMT) is shipping its first product, a 19nm DRAM line. -China is expanding into compound semis, including gallium nitride (GaN) and silicon carbide (SiC). -China’s OSATs are developing more advanced packages.
About 20 years ago China started developing its own 3G flavour as a way to develop its technology and to catch up. People were saying that they were quite far behind and that this might only sell in China (which it mostly did).
But today we see the result of this long term investment with Chinese companies front and centre in cellular an 5G.
I feel that chip manufacturing has shot up to an even higher priority for them now, so I'm thinking that the landscape may look very different from now in 20 years...
So I think everything is good til 2030.
Engineering in the billionths of a mm, alien technology to anyone born when I was born in 1980.
If you want to compare manufacturing processes then simply compare transistor densities. That way you will avoid the paradox of thinking that the physical limitations of an old transistor design apply to a chip that is using a completely different design. Here is a list of different possible designs [0].
[0] https://www.extremetech.com/wp-content/uploads/2019/05/FET-T...
There are really a lot of density boosters on the table to move the industry to N1 without much actual physical scaling.
Buried metal, CMOS-on-MOS, cells micro-optimisation, high-k on more things, vertical GAA...
If they can get to 0.5 na on 3500, then you don't even need to double pattern to reach N1 with all of the above
wikichip has five nodes listed under "5 nm lithography process", two of which are TSMC's:
- N5
- N5P
so N1 would be a hypothetical future process that can produce '1nm' "features".
I feel like I've been seeing these "can't shrink further very soon" claims (including the claim of hard, insurmountable physical limits) for about as long as fusion was 20 years away.
Times of crisis are also interesting, maybe intel will have to find new ideas to get his status back.
That had a diverse portfolio 25 years ago. They sold all of it off and now only have a handful of money makers.
Nice timing.