Oh, nice paper! I had been looking at this one, also by Matthew Pillmeier: https://preserve.lehigh.edu/cgi/viewcontent.cgi?article=1714...

I have a verilog module that implements the "Mux-Based Data Reversal" design with overflow output. Yosys/nextpnr synthesize it with a 102MHz timing estimate on the lattice ice40hx8k.

As for the 74F design, yeah, it uses the logarithmic approach. It still has massive multiplexers, but there's only 5 stages for a full 32 bit shift, plus the extra gates to handle the carry bit.