Edit: oops, after further investigation it looks like you may be doing this in your design?
I have a verilog module that implements the "Mux-Based Data Reversal" design with overflow output. Yosys/nextpnr synthesize it with a 102MHz timing estimate on the lattice ice40hx8k.
As for the 74F design, yeah, it uses the logarithmic approach. It still has massive multiplexers, but there's only 5 stages for a full 32 bit shift, plus the extra gates to handle the carry bit.
In terms of speed, you'll find that LVC at 3.3V is likely to outperform F at 5V, and AUC at 3.3V will definitely outperform everything short of ECL -- the catch there is that AUC is technically not specified for 3.3V operation. To stay at 5V, LVC is a good choice if available in the functions you need (LVC is maddeningly inconsistent in that some parts run at 3.6V max and others at 5V max), or look around at the various high-speed families otherwise. The big bus drivers in ABT are great if they're available.
LVC is awesome, but that's the problem I've run into. Even with 74F there are a lot of functions missing, but the options are better.