Intel docs say this on CPU behaviour:
https://software.intel.com/content/www/us/en/develop/downloa...
[4.8 ACCESSED AND DIRTY FLAGS]
Memory-management software may clear these flags when a page or a paging structure is initially loaded into physical memory. These flags are “sticky,” meaning that, once set, the processor does not clear them; only software can clear them.
A processor may cache information from the paging-structure entries in TLBs and paging-structure caches (see Section 4.10). This fact implies that, if software changes an accessed flag or a dirty flag from 1 to 0, the processor might not set the corresponding bit in memory on a subsequent access using an affected linear address (see Section 4.10.4.3). See Section 4.10.4.2 for how software can ensure that these bits are updated as desired.
[4.10.4 Invalidation of TLBs and Paging-Structure Caches]
[4.10.4.2 Recommended Invalidation]
... so, I guess, yeah, this doesn't really help :|