Edit: Gate Array Logic, thanks everyone
As an example, if you have a very simple design with a 32k rom chip and a 32k ram chip, address decoding - controlling which chip is going to provide that address, is dirt simple. You take the highest bit of the address and use it as the enable line on one chip. Then you run the same signal through a NOT gate, and provide it as the enable to the other. So for addresses 0x0000 through 0x7fff, the high bit is 0, and one chip is enabled, and for addresses 0x8000 onwards, the high bit is 1, and the other chip is enabled instead. So when I address 0x8000, I'm actually addressing location 0 on the 2nd chip.
But when you look at contemporary designs, 32k & 64k ram chips were either unavailable, or an unnecessary expense. It's not unusual to see old-school devices with a whole cluster of 1k ram chips - and my nice, understandable decoding starts to get expensive. Now you're trying to compare the top 6 address bits, with lots of replication for each ram chip. If I were to do it, I'd probably use two 74138 chips to do binary-to-decimal, and then an AND gate per ram chip to compare the outputs. For 32k of ram, and at 4 AND gates per 7408, we end up with 2x74138 and 8x7408.
So as a hobbyist, I'd much prefer this as I can still describe the entire process end-to-end. For mass-production, replacing 10 discrete-logic chips with one programmable-logic chip, is several wins.
Commonly used to replace 74xxx chips they do glue logic in classic 8bit computer designs like the Apple II