With 5nm coming soon, I think this is inevitable. It's now possible to put 127M transistors in a single square millimetre, but despite billions of transistors in a CPU, total performance is not hundreds of thousands of times greater than primitive CPUs from decades ago.
It would cost next to nothing in terms of chip area to have a simple "controller" CPU in each DRAM chip that can issue vector instructions without needing to have its hand held.
The problem is the instruction set: where do you stop? Do you just have simple logic operations, or a full set of floating point operations? Do you have flow control? Stacks? Etc...
Code would either have to be written in the "full featured" language as well as a cut-down language similar to CUDA, or the embedded little chips would have to be full CPUs.
The other issue is cache coherence. It's possible to have designs where either the little DRAM CPUs participate or they don't. Both have big advantages and big disadvantages, and neither is easy.
I suspect that this is going to start turning up in GPUs before CPUs, or possibly for HPC applications before general purpose computers.