You don't know true embedded BDSM until you've debugged incorrect timing constraints on an FPGA ... with a customer on the other side of the planet ... only to realize later that they have no idea how to design an HDMI compliant board and none of it was your own fault.
Or spending three weeks trying to achieve timing closure on a design, only to finally realize after much inspection of the routed designs by myself and an IntelFPGA FAE that the router was smoking digital crack the whole time and had no clue how to route their own divider units?
Or maybe the programming facility reversed bit ordering on a batch of the FPGA's flash chips and you only learn of that after a very, very long couple of nights of language barrier back and forth with a flummoxed customer.
The joys are endless.