So if Intel actually stayed on track for this roadmap, they're saying "we only have 10 years left to advance our fabs". Unless 1.4nm is actually meaningless, they'd be edging up to electron tunneling issues with a contacted gate pitch of ~10 atoms across.

I'm being optimistic with this guesswork. Intel's historical naming is that cpp = 3-5x node name [1]. Silicon lattice spacing is ~0.54nm.

[1] https://en.wikichip.org/wiki/intel/process